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https://www.phoronix.com/scan.php?page=news_item&px=GCC-10-Emulating-MMX-With-SSE
May 17, 2019 · The GCC 10 code compiler merged support to begin emulating MMX intrinsics using SSE. Back in February we wrote about the patches by Intel for implementing MMX intrinsics using SSE instructions.For those still relying upon MMX SIMD instructions, the benefit of implementing it using SSE is that it frees up an 8-byte vectorizer for SSE2 when MMX is …
https://gcc.gnu.org/onlinedocs/gcc-9.2.0/gcc/x86-Options.html
3.18.58 x86 Options. These ‘-m’ options are defined for the x86 family of computers.-march=cpu-type Generate instructions for the machine type cpu-type.In contrast to -mtune=cpu-type, which merely tunes the generated code for the specified cpu-type, -march=cpu-type allows GCC to generate code that may not run at all on processors other than the one indicated.
https://www.phoronix.com/scan.php?page=news_item&px=GCC-MMX-Intrinsics-With-SSE
The benefit when disabling MMX in 64-bit mode is that an 8-byte vectorizer is enabled with SSE2 but likely they are getting ready to permanently retire native MMX support in future processors. Details on this pending patch series for GCC 10 can be found on their mailing list. Emulating all of the MMX instructions with SSE plus the test coverage ...
https://gcc.gnu.org/onlinedocs/gcc-5.4.0/gcc/x86-Options.html
In contrast to -mtune= cpu-type, which merely tunes the generated code for the specified cpu-type, -march= cpu-type allows GCC to generate code that may not run at all on processors other than the one indicated. ... Intel Pentium CPU with no MMX support.
https://berthub.eu/gcc-simd/example.html
These are described in the X86 Built-in functions and PowerPC Altivec Built-in functions chapters of the gcc manual. And lastly, gcc has recently gained intrinsic support for some SIMD operations whereby the coder requests a vector of specified dimension and content, and then performs operations on that vector.
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